`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Yu Zihao
// 
// Create Date: 2021/08/01 16:37:55
// Design Name: 
// Module Name: alu_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
//    Value on ALUop input  |  Operation
//           00             |  Ain + Bin
//           01             |  Ain - Bin
//           10             |  Ain & Bin
//           11             |    ~Bin
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module alu_tb();
    reg [15:0] Ain, Bin;
    reg [1:0] ALUop;
    wire [15:0] out;
    wire N,V,Z;
    //-32768~32767
    initial begin
    ALUop = 2'b00;
    Ain = -16'd32768; Bin = -16'd1;
    #10
    Ain = 16'd32767; Bin = 16'h1;
    #10
    Ain = 16'd32760; Bin = 16'h51;
    #10
    Ain = 16'h0; Bin = 16'h0;
    #10
    ALUop = 2'b01;
    Ain = 16'd50; Bin = 16'd60;
    #10
    Ain = 16'd32760; Bin = -16'd30;
    #10
    Ain = -16'd30; Bin = 16'd32760;
    #10
    Ain = -16'd30; Bin = -16'd30;
    #10
    ALUop = 2'b10;
    Ain = 16'h1; Bin = 16'h7FFF;
    #10
    Ain = 16'hFFFF; Bin = 16'h2;
    #10
    Ain = 16'h5; Bin = 16'h51;
    #10
    Ain = 16'h0; Bin = 16'h0;
    #10
    ALUop = 2'b11;
    Ain = 16'h1; Bin = 16'hFFFF;
    #10
    Ain = 16'hFFFF; Bin = 16'h2;
    #10
    Ain = 16'h5; Bin = 16'h51;
    #10
    Ain = 16'h0; Bin = 16'h0;
    #10
    $stop;
    end

    ALU alu0(Ain,Bin,ALUop,out,N,V,Z);
endmodule
